کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
865810 909682 2008 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Incremental Placement-Based Clock Network Minimization Methodology
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه سایر رشته های مهندسی مهندسی (عمومی)
پیش نمایش صفحه اول مقاله
Incremental Placement-Based Clock Network Minimization Methodology
چکیده انگلیسی
Power is the major challenge threatening the progress of very large scale integration (VLSI) technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Tsinghua Science & Technology - Volume 13, Issue 1, February 2008, Pages 78-84
نویسندگان
, , , ,