کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
865990 | 909690 | 2007 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Arithmetic Operand Ordering for Equivalence Checking
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موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی (عمومی)
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Arithmetic Operand Ordering for Equivalence Checking Arithmetic Operand Ordering for Equivalence Checking](/preview/png/865990.png)
چکیده انگلیسی
An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZD_VIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Tsinghua Science & Technology - Volume 12, Supplement 1, July 2007, Pages 235-239
Journal: Tsinghua Science & Technology - Volume 12, Supplement 1, July 2007, Pages 235-239
نویسندگان
Weng (ç¿å»¶ç²), Ge (èæµ·é), Yan (严æ浪), Ren (ä»» å¤),