Analog, parallel, sorting circuit for the application in Neural Gas learning algorithm implemented in the CMOS technology

The paper presents a novel circuit, implemented in the CMOS technology, that allows for sorting analog signals in parallel. The circuit is to be used in neural networks trained in accordance with Neural Gas (NG) learning algorithm implemented in the CMOS technology. The role of the circuit is to determine, for a given learning pattern, the winning neuron as well as its neighbors. The proposed circuit is versatile. It can be also used, for example, in nonlinear filtering of analog signals. It is capable of performing simultaneously several typical nonlinear operations that include Min, Max and median filtering. The circuit offers high accuracy, which means that it is able to distinguish signals which differ by a relatively small value. However, the accuracy depends on the calculation time. For example, to be able to distinguish the signals that differ by 10 nA (for maximum range of 10 µ A), the assumed calculation time has to be set to at least 1 µ s. To improve the accuracy to 5 nA, the calculation time has to be doubled. The circuit provides us the sorted list of signals, in accordance with their values. This information contains both the positions of the signals on the sorted list and their values. The first parameter is used in the NG learning algorithm. The circuit was implemented in the TSMC 180 nm CMOS technology and verified by means of the corner analysis in the HSpice environment. For an example case of eight inputs varying in between 1 to 10 µ A the circuit dissipates an average power of 300 µ W, at data rate of million sorting operations per second.