Multiple voltage and frequency scheduling for power minimization

The design description for an integrated circuit may be described in terms of three domains, namely: (1) behavioral domain, (2) structural domain and (3) physical domain. These domains may be hierarchically divided into several levels of abstraction. Classically, these level of abstraction are (1) Architectural or Functional level, (2) Register-transfer level, (3) Logic level and (4) Circuit level. Some of the design problems associated with VLSI circuit design are area, speed, reliability and power consumption. With the development of portable devices, power consumption has become a dominant design consideration in the modern VLSI design area. In each of these domains there are a number of design challenges to reduce power. For instance, at the behavioral level, the freedom to choose multiple voltages and frequencies to minimize power to meet the given hard time constraints is considered as an active field of research to minimize power. Various past researches have showed that higher the level of abstraction, better the ability to address the problems associated with the design. Therefore this work proposes an algorithm that allocates both voltage and frequency simultaneously to the operations of the directed flow graph to optimize power given the time constraints. The resources required for multiple voltage-frequency scheduling is derived using the classical force directed scheduling algorithm. This algorithm has been implemented and tested on High-Level synthesis benchmarks for both non-pipelined and pipeline instances.