FPGA based EBCOT architecture for JPEG 2000

In this paper a high speed FPGA based implementation of Embedded Block Coding with Optimized Truncation (EBCOT) algorithm used in JPEG 2000 is proposed and implemented. The context formation engine used in EBCOT is analyzed and an architecture based on parallel processing of the three coding passes is proposed. A three stage pipelined architecture for the Arithmetic Encoder is used to speed up the encoding. When implemented on a XC2V1000 device, the design performs at 50 MHz after place and route. Processing time is reduced by more than 75% compared to sample based implementation and by more than 34% compared to the best architecture known.