Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models

As the technology node continues to scale, soft errors have become a major issue for reliable processor designs. In this paper, we propose a framework that accurately and efficiently estimates the Architectural Vulnerability Factor (AVF) of critical storage structures of a processor. The proposed approach exploits the masking effects between array structure (e.g., register files and Caches) and logic units (e.g., Int-ALU) via the unified Probabilistic Graphical Models (PGM) methodology, and can provide guaranteed AVFs by two accuracy-efficiency tradeoff solutions. The experimental results have confirmed that, compared to current state-of-the-art approaches, the proposed framework achieves accurate and efficient estimation via two instanced solutions: (1) first-order masking effects up to 45.96% and on average 8.48% accuracy improvement with 52.01× speedup; (2) high-order masking effects average 87.28% accuracy improvement with 43.87× speedup. The two different accuracy-efficiency tradeoff of proposed MEA-PGM can be applied into different estimation scenarios (e.g., short time to market of general mobile devices and high reliable requirements in aerospace platforms) in flexibility.