FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies

• We have performed automatic discrete nominal sizing of 14nm FinFET-based logic cells
• The impact of global and local process variations on logic cells for FinFETs using TCAD and PTM models has been studied
• The influence of TDDB on cell performance has been studied

Technology scaling has an increasing impact on the resilience of integrated circuits. This leads to the necessity of using new technology-level innovations, such as employing FinFET instead of planar transistors. For such novel devices, performance characteristics, reliability and variability behave potentially different, compared to planar devices. This paper explores different sources of process variations in 14 nm technology node and studies their impact on FinFET-based circuit designs. Both TCAD and PTM device models are used and compared with regard to the performance metrics of the circuits. This reveals insights into the behavior of future technology generations. Reliability and variability will be considered.