کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
10365323 872037 2005 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
TLP analysis of 0.125 μm CMOS ESD input protection circuit
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
TLP analysis of 0.125 μm CMOS ESD input protection circuit
چکیده انگلیسی
In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a secondary ggNMOS clamp in the input protection circuitry, then the trigger voltage, Vt1, of the ggNMOS clamp is not a constant. The value is influenced by the size and properties of the input resistor, by current injection problems due to parallel resistive networks formed between the primary and secondary ESD circuits, by reverse bias diode leakage currents effects, and by source elevation effects due to voltage rises along the ESD ground bus.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 45, Issue 2, February 2005, Pages 223-231
نویسندگان
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