A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites

A highly scalable 2-bit nonvolatile memory (NVM) cell using two electrically isolated charge trapping sites is proposed and demonstrated by numerical device simulation. The operational mechanisms including read, program, erase and inhibit in an array structure are studied in detail. This double storage capability per single cell and highly scalable structure is very suitable for high density nanometric NVM applications.