The impact of PMOST bias-temperature degradation on logic circuit reliability performance

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product's speed (Fmax) and minimum allowed operating voltage (Vccmin). BT degradation occurs during the product Burn-In and under the normal circuit operation. The interaction of device degradation and circuit performance is explained. Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanism and degradation models are proposed to explain the interaction of fluorine with device and circuit reliability. Process optimization, such as fluorine implant, can be used to reduce the pMOST BT impact on circuit degradation. Reliability guardband in Fmax and Vccmin is recommended, as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime. A guardband methodology is also discussed in the paper.