Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well

In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 μm rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage Double-Diffusion NMOS (HV-DNMOS) from punching through was also suggested. The experimental results show the yields of the HV-PMOS and the HV-CMOS are more than 98% and 95%, respectively, which are due to adding the p-well to HV-PMOS for eliminating the influence of the lithography misalignment during etching the unwanted thick gate oxide film of the HV-PMOS and that to HV-DNMOS for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be well applied in high voltage driver ICs, etc.