CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors

In this paper, we propose a system-level analytical technique, called Component Error Derating And Read frequency (CEDAR) vulnerability model, combining the advantages of previously presented analytical models and the SFI techniques. The key idea behind CEDAR is to take into account component error derating and read frequency for data-path blocks in high-performance processors. To further investigate the impact of read frequency and component error derating on the system-level VF, we use Input-to-Output Derating (IOD) factor of system components in the proposed analytical model. As a case study, we study system-level vulnerability for cache memory by providing IOD analysis for different processor core configurations. Our experimental results reveal that processor core IOD can significantly affect the system-level vulnerability of cache memories. The experimental results show that CEDAR improves the accuracy of previous analytical VF estimation techniques up to 91% and 5% for write-through and write-back cache memories, respectively, while it speeds up estimation time up to 10× as compared to SFI techniques.