کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10633654 | 993050 | 2005 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Elemental devices, circuits and processes for a monolithic Si/III-V-N alloy OEIC
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی مواد
سرامیک و کامپوزیت
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چکیده انگلیسی
The fabrication process of elemental devices for novel OEICs were studied based on a Si/III-V-N alloy/Si structure. The elemental devices are MOS transistors and LEDs fabricated on a Si capping layer and III-V-N alloy layer, respectively. The fabrication process was simplified by combining the gate oxidation with the post-annealing of ion implantation and thermal annealing for increasing the light-emission efficiency of GaPN alloys. Surface inversion was observed in a MOS diode fabricated on a Si/GaPN/Si structure. A GaPN/GaP DH LED grown on a GaP substrate was fabricated as well. It was clarified that the elemental devices could be principally fabricated by a simplified fabrication process although several problems have to be overcome. Key issues are the reduction of N-related point defects, the doping control for the III-V-N alloy and Si layers and the reduction of the surface roughness of the Si capping layer.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Optical Materials - Volume 27, Issue 5, February 2005, Pages 799-803
Journal: Optical Materials - Volume 27, Issue 5, February 2005, Pages 799-803
نویسندگان
H. Yonezu, Y. Furukawa, H. Abe, Y. Yoshikawa, S.-Y. Moon, A. Utsumi, Y. Yoshizumi, A. Wakahara, M. Ohtani,