Design and analysis of low power memory using efficient charge recovery logic circuits

ECRL (efficient charge recovery logic) circuits can reduce the energy consumption compared with that of the static circuits. The ECRL circuits have been applied to the combination logic. However, storage elements are also required for most of digital circuits. A simple structure of an ECRL latch is proposed for a storage element. It consists of an ECRL inverter, an ECRL NAND gate, and two MOSFET switches, and it has input signals of `enable', `input', and `reset'. A 16 × 8-bit shift register file is designed using the latches and a specially designed power supply which generates 4-phase oscillatory waves. The efficiency of the energy consumption is improved by about 50% as the changing rates of the input values are decreased, and it is not affected by the power supply clock frequency in the range of 100-400 MHz. The energy consumption of the proposed circuit is about half of that of the static CMOS TSPCL (true single-phase clocked logic) register.