کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10706872 | 1023507 | 2005 | 8 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Unified low power optimization algorithm by gate freezing, gate sizing and buffer insertion
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
فیزیک و نجوم
فیزیک ماده چگال
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Unified low power optimization algorithm by gate freezing, gate sizing and buffer insertion Unified low power optimization algorithm by gate freezing, gate sizing and buffer insertion](/preview/png/10706872.png)
چکیده انگلیسی
One of the major factors contributing to the power dissipation in CMOS digital circuits is the switching activity. Many of such switching activities include spurious pulses, called glitches. In this paper, we propose a new method of glitch reduction by gate freezing, gate sizing, and buffer insertion. The proposed method unifies gate freezing, gate sizing, and buffer insertion into a single optimization process to maximize the glitch reduction. The effectiveness of our method is verified experimentally using LGSynth91 benchmark circuits with a 0.5 μm standard cell library. Our optimization method reduces glitches by 65.64% and the power by 31.03% on average.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Current Applied Physics - Volume 5, Issue 4, May 2005, Pages 373-380
Journal: Current Applied Physics - Volume 5, Issue 4, May 2005, Pages 373-380
نویسندگان
Hyungwoo Lee, Hakgun Shin, Juho Kim,