Impact of different transistor arrangements on gate variability

This paper evaluates a set of complex cells with different transistor arrangements that implement the same logic function. These cells were evaluated under nominal conditions and with gate variability at layout level. The purpose is to verify what topology is more appropriate to increase the robustness of cells regarding the process variability issues. Results emphasize the importance of investigating the effects caused by process variability in FinFET technologies, as the electrical characteristics of circuits suffer significant changes. In general, the best choice is to use the network that the transistor in series is as far as possible to the output node. However, a trade-off needs to be done due to performance and power consumption penalties.