Thermal behavior of floating gate oxide defects (moving bits)

The defect density of the oxides used in non-volatile memories (NVM) is a key parameter to the understanding of the data loss of these structures. One of the most critical phenomena responsible for this loss (in the range of oxide thicknesses used in NVM devices) is the stress induced leakage current (SILC). The origin of SILC is generally attributed to the trap assisted tunnelling (TAT); therefore, a better understanding of the evolution of the oxide defects is necessary. It is known that the leakage through the oxide defects is temperature accelerated below 100 °C. Besides, it was observed that above 100 °C, the oxide defects are annealed. To better understand the temperature behavior of the defect population, a dedicated method has been devised and applied to several baking experiments. It leads to new observations and to the correction of some biased interpretations due to unsuitable experimental methods. Indeed, in this paper, we point out the fact that the annealing effect already occurs at 60 °C. The activation energy was calculated and found independent from both the electrical field across the oxide and the number of program/erase (P/E) cycles. The temperature behavior of the leakage is found to be more complex than what was reported in the literature: it is a balance between two opposite phenomena. Based on that, a new model describing the defect population evolution is proposed.