Source/drain technologies for the scaling of nanoscale CMOS device

Continuous shrinking CMOS device into 21 nm technology node is facing fundamental challenges. The International Technology Roadmap for Semiconductors (ITRS) forecasts specific requirements to realize acceptable CMOS performance for the semiconductor industry. The innovations of various source/drain technologies are considered to be indispensable for the continuous scaling of CMOS device due to the requirements of high-performance and effective suppression of short channel effects. One of the key points is to realize ultra-shallow junction with steep concentration profile and low resistivity. There are many innovative solutions including advanced doping technologies and annealing technologies for ultra-shallow junction formation. Additionally, new source/drain structures such as raised source/drain and Schottky barrier metal source/drain, and advanced silicidation technologies also serve as the important options. The state-of-the-arts of these new technologies are extensively discussed from the view point of technical innovation and performance gain. Source/drain technologies are promising and active areas of device research down to 21 nm technology node and even beyond.

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