Mechanisms of stress generation within a polysilicon gate for nMOSFET performance enhancement

Local stressors techniques are extensively used in CMOS technologies starting with the 90 nm node to compensate the mobility loss induced by extensive scale down. The purpose is to generate some strain within the silicon channel to enhance carrier mobility. To achieve nMOS performance at the 45 nm node, gate stressors are required in addition to standard nitride liners. With this option, the stress generated within the gate is directly transmitted into the channel and more than 10% gain in saturation current is achievable on nMOS.Stress is generated within the polysilicon gate through annealing under a capping liner. After liner removal, a part of this stress is memorized within the gate material. Final gate stress depends on both polysilicon pre-treatments and liner properties.This paper deals with material studies performed on capping liners in parallel to tests on electrical devices. Important parameters to generate stress under capping are presented. This allows providing a simple model and guidelines for further optimization.