Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2–GaAs metal–oxide–semiconductor devices

This work deals with the fabrication of a GaAs metal–oxide–semiconductor device with an unpinned interface environment. An ultrathin (∼∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO2. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO2/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.

► An interface passivation layer of ZnO on GaAs can control the interface trap densities and prevent the Fermi level pinning.
► Incorporation of ZnO interface passivation layer in GaAs MOS devices reduces gate leakage current.
► ZrO2/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.
► A ZrO2/ZnO stack is found to be a potential gate dielectric for GaAs based MOS devices.