TEM study of PtSi contact layers for low Schottky barrier MOSFETs

We report investigations of the silicide formation process in the Pt/Si structure of low Schottky barrier MOSFETs on SOI. The silicide layers are used there as source and drain contacts and the high quality of the silicide/Si interface and the silicide structure are essential for the electrical properties of the device. The platinum silicide is formed by the solid-state reaction between 15 nm thick Pt metallisation and a Si substrate during the annealing by the rapid-thermal-annealing (RTA) process at various temperatures (300, 400 and 500 °C). Cross-sectional transmission electron microscopy (XTEM) specimens were used to study the formation of the platinum silicide. The studies enabled the determination of the silicide layer thickness and morphology, as well as the silicide/Si interface roughness. The silicide layer for all investigated temperatures consists of a single layer of the silicide grains placed side by side. After annealing at 300 °C the grains are irregular in shape, while after 400 °C the shapes of the most of grains are regular, visible as squares or rectangles in a cross-section. After annealing at 500 °C the elongated grains due to the grain coalescence are mostly observed. The thickness of the silicide layer after annealing at 300 and 400 °C is about 29–30 nm. After annealing at 500 °C, the thickness changes and equals from about 27–28 nm at grain boundaries, to about 32–35 nm in the middle of grains. The roughness of the silicide/Si interface increases with the annealing temperature. The diffraction techniques were used to identify the silicide phase. The diffraction analysis showed that only the PtSi orthorhombic phase is formed in all studied samples.