Correlation between set and reset voltages in resistive RAM cells

• Observed dependence of Vset on Vreset in ReRAM cells and vice versa observed and explained.
• Modeling confirms Chua's postulate to describe memristors in terms of time integral over the voltage stress history.
• Simple model explains dependence of Vreset on voltage ramp rate including dependence on the on-state resistance.
• Analysis indicates a possible sensitivity of Vreset to details of programming pulse shapes.
• Gives insight how Vset and Vreset distributions could be tightened.

A positive correlation between set voltage, Vset, and the preceding reset voltage, |Vreset|, has been observed in resistive RRAM memory arrays and explained in terms of mechanisms responsible for forming and rupturing of the conductive Cu filament. This correlation can be reproduced on a single device by generating a spread in Vreset values by varying the linear voltage ramp rate. The dependence of Vreset on voltage ramp rate can be modeled by assuming that critical Joules heat is needed to trigger the rupture of the filament. Mechanisms are proposed to explain why higher |Vreset| necessarily leads to a higher Vset value during a subsequent set operation. The resulting dependence of Vset and Vreset on the voltage ramp rate during the reset operation can be used to tighten Vset and Vreset distributions, by applying low voltage ramp rates to cells with high Vset and high ramp rates to cells with low Vset values.