Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices

• Negative capacitance using ferroelectric materials is experimentally verified.
• A simple connection of negative capacitor to CMOS device enables to achieve sub-60 mV/decade SS.
• Details on the fabrication steps of the negative capacitor are fully disclosed.

In this study, an experimental study of negative capacitance is performed in order to overcome the physical limit of subthreshold slope (SS), SS ≥ 60 mV/decade at 300 K, which is originated from (i) using the thermionic emission process in complementary metal-oxide-semiconductor (CMOS) technology and (ii) non-scalability of the thermal voltage kBT/q (i.e., in order to realize SS lower than 60 mV/decade at 300 K). To make the surface potential higher than the gate voltage, a step-up voltage amplifier is included in the CMOS gate stack using a ferroelectric capacitor implemented with ferroelectric material. The measured SS in long-channel CMOS transistors is 13 mV per decade at 300 K. A simple connection of the ferroelectric capacitor to a complementary metal oxide semiconductor (CMOS) gate electrode would provide a new evolutionary pathway for future CMOS scaling.