A unified GFSK, π/4-shifted DQPSK, and 8-DPSK baseband controller for enhanced data rate Bluetooth SoC

For transmission of multimedia data via ad-hoc networks, the next-generation Bluetooth specification, Bluetooth EDR (Enhanced Data Rate) was developed recently. The design issues of the Bluetooth EDR are how area-efficiently three modulation schemes-GFSK, π/4-shifted DQPSK and 8-DPSK-are combined, and how fast and simply they perform seamless timing and carrier recovery as the demodulation scheme is changed to receive enhanced-rate data. So we proposed 6 hardware or software schemes for area reduction and simple implementation, and designed a Bluetooth EDR baseband controller using those schemes. We especially proposed and designed a simple scheme that compensates carrier frequency offset by using an average of phase errors between adjacent symbols. The FPGA implementation integrated with link manager software was tested with Bluetooth EDR specification, and was shown to be fully functional with enhanced data rates of 2 Mbps and 3 Mbps in spite of switching of modulation method during packet transmission. Timing recovery was completed within 10 μs which is shorter than 11 μs assigned to synchronization sequence after GFSK demodulation, and the coverage of frequency offset was 100 kHz which is wider than 40 kHz of the specification.