Use of negative capacitance to simulate the electrical characteristics in double-gate ferroelectric field-effect transistors

The surface potential and drain current of double-gate metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistor were investigated by using the ferroelectric negative capacitance. The derived results demonstrated that the up-converted semiconductor surface potential and low subthreshold swing S = 34 (<60 mV/dec) can be realized with appropriate thicknesses of ferroelectric thin film and insulator layer at room temperature. What's more, a reduction gate voltage about 260 mV can be reached if the ON-state current is fixed to 600 μA/μm. It is expected that the derived results can offer useful guidelines for the application of low power dissipation in ongoing scaling of FETs.

► The surface potential and drain current of field-effect transistor were investigated.
► The ferroelectric negative capacitance was considered in this investigation.
► A low subthreshold swing S = 34 (<60 mV/dec) can be realized with appropriate tf and ti.
► A reduction gate voltage about 260 mV can be reached if ION is fixed at 600 μA/μm.