Development of a versatile and modular test system for ATLAS hybrid pixel detectors

The insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USB-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed.