Use of fractional packet counting for high dynamic range imaging applications

An asynchronous self-reset with residue conversion scheme for the readout electronics of an image sensor, further referred to as Fractional Packet Counting (FPC), is proposed. The basic concept of the FPC is to increase the resolution of the conversion both by using a switched integrator and by quantifying its output at the end of the signal integration time. A circuit implementing this principle for CT applications is proposed and simulated. In particular, in the proposed circuit a constant relative resolution is used: this means to use floating point representation with a constant number of significant bits. Simulations show that a dynamic range of 117 dB is achieved, working at 2 kHz frequency. The detectable signal range goes from 24 fA to ∼400nA. The simulation results have been used to develop a mathematical model for the SNR accounting the different noise sources. The model shows that the floating point representation has no visible impact on the SNR of the circuit.