کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
1825541 | 1027365 | 2011 | 4 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
2D and 3D CMOS MAPS with high performance pixel-level signal processing
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
فیزیک و نجوم
ابزار دقیق
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130Â nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130Â nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130Â nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment - Volume 628, Issue 1, 1 February 2011, Pages 212-215
Journal: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment - Volume 628, Issue 1, 1 February 2011, Pages 212-215
نویسندگان
Gianluca Traversi, Luigi Gaioni, Massimo Manghisoni, Lodovico Ratti, Valerio Re,