Development of a low-noise, two-dimensional amplifier array

This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-noise requirement of better than 100e-100e- (rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4×44×4 matrix of identical 270μm×270μm pixel cells and was implemented with TSMC 0.35-μm0.35-μm CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e-88e- (rms) equivalent noise charge and a 25e-/pF25e-/pF noise slope with power consumption of 150μW per pixel.