An associative memory-based learning model with an efficient hardware implementation in FPGA

In this paper we propose a learning model based on a short- and long-term memory and a ranking mechanism which manages the transition of reference vectors between the two memories. Furthermore, an optimization algorithm is used to adjust the reference vectors components as well as their distribution, continuously. Comparing to other learning models like neural networks, the main advantage of the proposed model is that a pre-training phase is unnecessary and it has a hardware-friendly structure which makes it implementable by an efficient LSI architecture without requiring a large amount of resources. A prototype system is implemented on an FPGA platform and tested with real data of handwritten and printed English characters delivering satisfactory classification results.

Research highlights
► A learning model based on a short and long-term memory and a ranking mechanism is proposed.
► Pre-training phase is unnecessary and the model has a hardware-friendly structure.
► The system is implemented on FPGA and tested with real data of handwritten and printed English characters.
► We are planning to use a fully-parallel associative memory implemented in an LSI architecture.