Improving static techniques for the analysis of voltage stability

The currently available dynamic techniques for the analysis of voltage stability are truly accurate but also expensive in terms of computation time. With the objective of overcoming such a disadvantage, several static techniques have been developed. Unlike conventional dynamic techniques, they share the advantage of drastically reducing computation time. However, they have disadvantages as well since they can not achieve results as accurately as conventional dynamic techniques do, fact admitted by the great majority of their authors. Another disadvantage is that since they are static techniques and therefore no time is involved, they can not control the chronological sequence of post-disturbance events. That is, if the power system succeeds in remaining stable after disturbance, then different time delay control devices can activate. What is more, any of these devices can stimulate the action of others producing in consequence a chain of post-disturbance events, which must not be ignored. A static technique for the analysis of voltage stability is proposed in the present paper. This technique shows higher accuracy in comparison with those currently available while keeping a reduced computation time. For this to be possible, modifications on the conventional Power Flow study are carried out, which includes a detailed modeling of the devices that are part of the power systems and a control of the chronological sequence of post-disturbance events through different time delay control devices.