Improved SVPWM vector selection approaches in OVM region to reduce common-mode voltage for three-level neutral point clamped inverter

• An improved Analytical SVPWM model to reducing CMV developed in this paper.
• 1st, the partial elimination of CMV with more voltage gain is achieved.
• 2nd, full elimination of CMV with more voltage gain with zero CMV is achieved.
• The Proposed algorithms does not require any additional calculations to operate the inverter in the OVM.
• The FPGA based hardware corroboration have shown the superiority of the proposed technique over the existing SVPWM schemes.

Multilevel inverters (MLIs) have an essential portion in industrial applications. Eventhough there are various elementary developments in MLI and its pulse width modulation (PWM) control strategies, unfortunately those strategies are least bothered about the common mode voltage (CMV). The CMV appears at the neutral point of the motor’s star connected stator windings with respect to the source ground. This study proposes PWM schemes for three level diode clamped multilevel inverter (DC-MLI) which use an unpretentious switching sequence to determine the triangle for maximum output voltage and minimum CMV in entire modulation range. Here two types of approaches are proposed: (i) Partial elimination SVPWM (PE-SVPWM) and (ii) Full elimination (FE-SVPWM). The proposed strategies suggest switching selection by using the control degree of freedom available in SVPWM without affecting the inverter output voltage. As a result, CMV reduction and elimination with maximum output voltage and better THD is achieved. The proposed PWM approaches can be extended for any number of levels. The theoretical study, the MATLAB/Simulink software based computer simulation and Field Programmable Gate Array (FPGA) SPARTAN-III-3AN-XC3S400 processor supported hardware corroboration have shown the superiority of the proposed technique over the existing SVPWM schemes.

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