Parallel solution of Newton’s power flow equations on configurable chips

The conventional Newton’s method (also known as Newton–Raphson method) for the AC power flow problem is preferred in some situations due to its local quadratic convergence. However, its high computation and memory requirements due to the required LU factorization of the Jacobian matrix at each iteration limit its practical employment in the online operation of very large systems. We produce here a novel partitioning scheme for the nonsymmetric Jacobian matrices appearing in the Newtons’s method. It results in the efficient parallelization of LU factorization and the subsequent solution of the power flow equations. We also present our implementation on our target computing platform comprising a single-chip shared-memory configurable multiprocessor. We designed and implemented our multiprocessor on an SOPC (system-on-a-programmable-chip) computer board containing an FPGA (field-programmable gate array) device. This new configurable computing paradigm combines the flexibility of microprocessors and programmable logic with the high performance of ASIC (application-specific integrated circuit) designs, and facilitates low-cost parallel implementations with reasonable turnaround times. Our good performance results for IEEE power test systems and others representing parts of the US power grid in the northeast demonstrate that our cost-effective and robust approach is viable and has tremendous potential to be enhanced further with steady advances in silicon technology, as predicted by Moore’s Law.