A massively parallel pipelined reconfigurable design for M-PLN based neural networks for efficient image classification

Weightless Neural Networks (WNNs) are a powerful mechanism for pattern recognition. Aiming at enhancing their learning capabilities, Multi-valued Probabilistic Logic Nodes (M-PLN) are used, instead of crisp neurons with a 0/1 based RAM-nodes. An M-PLN stores a mapping of, or possibly, the triggering probability, for each input pattern that needs to be recognized. The M-PLN model attempts to strengthen the discrepancies between distinct patterns used during the training process and those that have not yet been processed. In this paper, an efficient yet customizable hardware architecture for M-PLN based neural network is proposed. It implements the learning and operation processes of a pyramidal network structure, augmented by a probabilistic rewarding/punishing search algorithm. The training algorithm can adapt itself to the overall hit ratio so far achieved by the network. Using class-dedicated layers, the hardware is able to handle image classification in parallel and thus, very efficiently. Furthermore, the classification process is performed in a pipelined manner so its stages never stop working until all input images are classified. Nonetheless, during network training, only one of these layers is activated. Last but not least, the architecture is customizable as its structure can be tailored in accordance to the application characteristics in terms of class number, pattern tuple size and image resolution. In order to evaluate the time and cost requirements of the proposed design, its underlying architecture was specified in VHDL and functionally tested. The presented results are two-fold: first, based on many functional simulations, estimated time and cost requirements are analyzed; second, to further assess the performance of the proposed the design, the VHDL model was synthesized to produce a semi-custom implementation on FPGAs. We also give an assessment of the quality of the entailed classification process. The architecture exhibits performance and reconfiguration capabilities that are very promising and encouraging towards the fabrication of a prototype on ASIC.