Non-overlapped implantation (NOI) MOSFET synapse and its implementation on supervised neural network

In this work, we have demonstrated the supervised learning in a silicon-based neural chip applied in pattern recognition. Each synapse in the neural circuit was implemented using analog non-overlapped implantation (NOI) MOSFET. This is a non-volatile memory (NVM) device capable to be implemented in an artificial neural network hardware under a supervised learning algorithm. The NOI synapse is fabricated using a 0.25 μm CMOS process but with the lightly doped drain (LDD) implantation omitted. The gate voltage of the NOI synapse serves as the neural input signal. Its weight depends upon the changes in the threshold voltage due to trapped charges in the NOI synapse. The channel current represents the synapse output defined as the product of the stored weight and the applied input. The learning rate (η) is influenced by different proportions of the stress time. The NOI synapse plasticity was demonstrated using a 4×3 neural array for perceptron application. Six input patterns were used for the learning algorithm in these NOI synapses. During the training process, the output signals were supervised and compared to the target by updating NOI synapse weights until the system converges. The experimental results from the silicon chips have proven that NOI synapse has the potential in the development of a high density neural network hardware.