Implementation of a CNN-based retinomorphic model on a high performance reconfigurable computer

The complexity of hardware design methodologies represents a significant difficulty for non-hardware focused scientists working on accelerating the simulation of complex bio-inspired applications. An emerging generation of electronic system level (ESL) design tools is been developed, which allow software–hardware codesign and partitioning of complex algorithms from high level language (HLL) descriptions. These tools, together with high performance reconfigurable computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of highly parallelizable algorithms. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, are analyzed. A model for the first synapse of the retina, based on a discrete-time sequential CNN architecture suitable for FPGA implementation proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results showed that, with a minimum development time, a 10×acceleration, when compared to the software emulation, can be obtained.