A simple programmable axonal delay scheme for spiking neural networks

The paper addresses the need for a compact axonal delay circuit for analogue hardware neural networks. The delay is implemented using the charging of a capacitive node via a pMOSFET operating in sub-threshold. The duration of the delay can be programmed by adjusting the associated MOSFET gate voltage and delays spanning five orders of magnitude, between microseconds and tens of milliseconds are shown experimentally. A model is reported that allows for prediction of the delay. This analysis is supported by experimental results from circuits fabricated in AMS 0.35 μm CMOS. An approach for integration of the axon circuit into a neuron circuit is also considered, where both single and burst spikes are possible.