Techniques for power reduction in an SIMD implementation of the VQ/SOM algorithms

Hardware implementations of the VQ (vector quantization) and SOM (self organizing map) permit the deployment of these computationally intensive algorithms as single chips or IP cores. This paper discusses the design of an IP core based on an SIMD (single instruction multiple data) processor array for such an implementation with emphasis on those aspects of the design which lead to a low power implementation. Power reduction techniques described are: local memory sharing between processors; processor instruction set and datapath organization; implementation of the winner take all calculation; and use of a thresholding algorithm to permit power down of processors during the distance calculation. It is shown that with a typical 0.13μm low power semiconductor process and with a clock speed of 100 MHz the power dissipation per processor is approximately 1 mW without use of thresholding. Including thresholding reduces this power to less than 0.5 mW per processor. Area for a 256 processor array with 256 8-bit vector elements per processor is 3.5 mm ×2.5 mm.