Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats

A practical brain-machine interface (BMI) requires real-time decoding algorithms to be realised in a portable device rather than a personal computer. In this article, a field-programmable gate array (FPGA) implementation of a probabilistic neural network (PNN) is proposed and developed to decode motor cortical ensemble recordings in rats performing a lever-pressing task for water rewards. A chronic 16-channel microelectrode array was implanted into the primary motor cortex of the rat to record neural activity, and the pressure signal of the lever were recorded simultaneously. To decode the pressure value from neural activity, both Matlab-based and FPGA-based mapping algorithms using a PNN were implemented and evaluated. In the FPGA architecture, training data of the network were stored in random access memory (RAM) blocks and multiply-add operations were realised by on-chip DSP48E slices. In the approximation of the activation function, a Taylor series and a look-up table (LUT) are used to achieve an accurate approximation. The results of FPGA implementation are as accurate as the realisation of Matlab, but the running speed is 37.9 times faster. This novel and feasible method indicates that the performance of current FPGAs is competent for portable BMI applications.