کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
439148 | 690460 | 2008 | 15 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
نظریه محاسباتی و ریاضیات
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چکیده انگلیسی
In this article, a verification methodology for mixed-signal circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Theoretical Computer Science - Volume 404, Issue 3, 28 September 2008, Pages 293-307
Journal: Theoretical Computer Science - Volume 404, Issue 3, 28 September 2008, Pages 293-307