Low-power pulsed hybrid flip-flop based on a C-element

This paper presents a new flip-flop design featuring implicit pulse-triggered structure in which a dynamic front-end stage and a static back-end one are adopted, thereby, it is considered as a hybrid flip-flop possessing both low-power and high-performance targets. Proposed flip-flop is implemented by a sampling circuit, a C-element for rise and fall paths, and a keeper stage. Simulation results in 45 nm CMOS technology with a 1 V supply voltage demonstrate that 27.8% and 16.9% reductions in terms of power consumption as compared to all other reported flip-flop designs in 25% and 50% data activities, respectively. Moreover, utilizing only four clocked transistors along with transition condition technique make proposed design fast and power-efficient in all activity factors, and exhibiting 5% enhancement in speed. Hence, other exploitable advantage of presented design is power-delay-product (PDPDQ) index whose improvement ranges from 16.7% to 56%. It is also indicated that presented scheme having negative setup time near zero and considrable hold time contains only 17 transistors severely affecting layout area efficiency being by as much as 12%. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance in power dissipation and PDPDQ metrics.