A divider-less, high speed and wide locking range phase locked loop

A high performance, high frequency phase-locked loop (PLL), based on a divider-less structure is presented in this paper. This PLL includes an open-loop phase frequency detector (PFD) and a bulk driven charge pump which is designed by utilizing a 0.18 μm CMOS process with a 1.8 V power supply. The proposed PLL has a locking range frequency of 2.5–7.3 GHz. The rms and peak-to-peak jitters of this PLL at 5 GHz are 3.21 and 0.88 ps respectively. The total power consumption is approximately 13.4 mW.