Analysis of chaotic behavior in pipelined analog to digital converters

This paper presents a new approach to analysis of chaotic behavior in pipelined analog to digital converters. To this end, the fundamental theorem for function of a random variable is exploited and the propagation of the output pdf of chaotic maps in successive stages of pipelined converter is shown. It is illustrated that 1-bit stage of this converter can be used to implement the Bernoulli map, and also the 2k-way Bernoulli shift map can be implemented using k × 1-bit stages or one k-bit stage. It is revealed that in the half-bit redundant structure, after a sufficiently large number of cycles, residue density becomes concentrated in the center half of the stage full-scale range. In this way, the 1.5-bit stage characteristic will be fully equivalent to the common chaotic map that is employed to generate random number sequences. By applying the proposed approach to the joint density of residue stages, it is shown that residues become independent and uniformly distributed. This feature is used to design multi bit chaotic random number generator using full-bit and half-bit redundant pipelined ADC structure. The validity of the proposed random number generator is confirmed by passing all NIST statistical tests even in the presence of nonidealities.