کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
447304 1443221 2009 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Partial error tolerance for bit-plane FIR filter architecture
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
Partial error tolerance for bit-plane FIR filter architecture
چکیده انگلیسی

Whereas some applications require correct computation many others do not. A large domain where perfect functional performance is not always required is multimedia and DSP systems. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. The goal of this paper is to develop a method for trading computational correctness for an additional chip area involved by fault-tolerance implementation. The method is demonstrated for the BP array in the following way: only the most significant bits of the output word are made fault-tolerant. By introducing the concept of partially error-tolerant BP array, designers achieve one more degree of tradeoff freedom. Formal definitions of the proposed terms are given. A mathematical path based on transitive closure that generates an error significance map for the BP array is proposed. The design tradeoff is demonstrated through FPGA implementation. The achieved area savings are presented as a function of a number of most significant fault-tolerant bits.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 63, Issue 5, May 2009, Pages 398–405
نویسندگان
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