FPGA implementation of vector directional distance filter based on HW/SW environment validation

In this paper a new FPGA implementation approach of vector directional distance filter (VDDF) using HW/SW solution is presented. The challenges of our solution include ease of implementation, good accuracy and relatively high speed. We use approximations to solve hardware limitations. HW/SW solution uses Nios-II FPGA development board. Experimental results using a number of color images show that the approximated VDDF achieves an excellent balance between computational speed and filtering quality. Moreover, the efficient design processes at 110 MHz system clock and gives a good execution time compared to the software based solution.