Voltage island based heterogeneous NoC design through constraint programming

• A two-stage Constraint Programming (CP) model was proposed for designing a heterogeneous Network-on-Chip (NoC).
• With shape, size constraints and proper assumptions, method was improved to solve Voltage-Frequency Island (VFI) problem.
• Our VFI implementation requires solving a single stage CP model.
• Real application data were used to conduct experimental studies to show the applicability of the models.

This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature.

Figure optionsDownload as PowerPoint slide