Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores

Application-Specific Network-on-Chip (ASNoC) synthesis has found increasing significance in developing System-on-Chip (SoC) solutions for applications. This paper integrates various issues in the ASNoC synthesis process – availability of soft cores (with area and aspect ratio regulations), floorplanning for the whole NoC and determining router locations. Apart from attaching primary routers to the cores, it also introduces necessary extra secondary routers, so that the inter-router link length can be kept within a specified upper bound. A Particle Swarm Optimization (PSO) based formulation has been made to solve this integrated problem with a trade-off between the overall chip-area and the network communication overhead. Experimentation has been carried out with a set of well-known benchmarks. Apart from static communication cost, throughput, latency and energy consumption of the approach have been computed. The approach compares favourably with some recent approaches reported in the literature.