کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
460894 | 696471 | 2008 | 12 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Design of a hardware accelerator for path planning on the Euclidean distance transform
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
This paper presents a novel hardware-directed algorithm for finding a path for a mobile robot using the Euclidean distance transform of the binary image of an environment. The robot can translate as well as rotate. The path obtained from start to goal is the shortest in terms of the number of steps. The mapping of the algorithm to hardware is described. Results of efficient implementation on a Xilinx FPGA device show that the device can be operated at a clock rate of about 65 MHz. Such a high frequency of operation leads to computing a collision-free path on sample images of size 128 × 128 in less than 3 ms and hence the hardware can process images at a video rate. This is necessary for real-time path planning in a dynamic environment.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Systems Architecture - Volume 54, Issues 1–2, January–February 2008, Pages 253–264
Journal: Journal of Systems Architecture - Volume 54, Issues 1–2, January–February 2008, Pages 253–264
نویسندگان
N. Sudha, A.R. Mohan,