Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve

Many novel and interesting cryptographic protocols have recently been designed with bilinear pairings comprising their main calculation. The ηT method for pairing calculation is an efficient computation technique based on a generalisation and optimisation of the Duursma-Lee algorithm for calculating the Tate pairing. The pairing can be computed very efficiently on hyperelliptic curves of genus 2. In this paper it is demonstrated that the ηT method is ideally suited for hardware implementation since much of the more intensive arithmetic can be performed in parallel in hardware. A Tate pairing processor is presented and the architectures required for such a system are discussed. The processor returns a fast pairing computation when compared to the best results in the literature to date. Results are provided when the processor is implemented on an FPGA over the base field F2103.