MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture

• The proposed work consists of four stages, namely selection, analysis, and design and performance comparison.
• First stage – various sense amplifiers are selected for further processing.
• Second stage – selected sense amplifiers (M-DTSA, MCG-DTSA, MDET-DTSA, S-DTSA) are applied with various traffic rates.
• Third stage – reconfigurable DTSA for complete transceiver is designed.
• Fourth stage – performance comparison is made between proposed and conventional approaches.

Now-a-days there is much research attempts aim to find out low power consumption in the area of Network-on-chip (NoC), both in architectural as well as algorithmic approach. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy than its indented design during heavy traffic condition. Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture (MATHA) is designed in this research to eliminate the difficulty. This MATHA is a combination of reconfigurable DTSA and transceiver. The reconfigurable DTSA consist of modified DTSA (M-DTSA), modified clock gating with DTSA (MCG-DTSA), Modified Dual Edge Triggered with DTSA (MDET-DTSA), Soft-DTSA (S-DTSA), graph theory based traffic estimator and multiplexer. Depending upon the traffic rate, one of the DTSA among the available four DTSA is selected and information transferred to the receiver. The proposed MATHA design is evaluated on TSMC 90 nm technology, showing 6.1 GB/s data rate and 0.32 W total link power.

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